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The Impact of Domain Crossing on Safety
Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for...
View ArticleClock Domain Crossings in the FPGA World
Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC issues on design functionality grows...
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Adding Order And Structure To Verification
You can’t improve what you can’t measure, and when it comes to methodologies the notion of measurement becomes more difficult. Add in notions of the skills, capabilities and experience levels of...
View ArticleClik here to view.
FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis...
Increasing power constraints have resulted in finer-grained partitioning of designs into functional domains that can have clocks disabled or, more drastically, are powered down entirely. Systems are...
View ArticleSignoff-Compatible CDC
Tanveer Singh, senior staff consulting applications engineer at Synopsys, explains why netlist clock domain crossing is now an essential complement to RTL CDC, why CDC issues are worse at advanced...
View ArticleClik here to view.
Clock Domain Crossing Signoff Through Static-Formal-Simulation
By Sudeep Mondal and Sean O’Donohue Clocking issues are one of the most common reasons for costly design re-spins. This has been the driving factor in the ever-increasing demand for Clock Domain...
View ArticleClock Domain Crossing Technology Workshop 2019
The post Clock Domain Crossing Technology Workshop 2019 appeared first on Semiconductor Engineering.
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Shift Left Power-Aware Static Verification
Next-generation SoCs with advanced graphics, computing, machine learning (ML) and artificial intelligence (AI) capabilities are posing new unseen challenges in Low Power Verification. These techniques...
View ArticleUPF-Aware Clock-Domain Crossing
Synopsys’ Namit Gupta talks with Semiconductor Engineering about low-power design techniques at the most advanced process nodes, including how to verify the impact of CDC on power at the register...
View ArticleHierarchical CDC verification with Alint-PRO (EU)
The post Hierarchical CDC verification with Alint-PRO (EU) appeared first on Semiconductor Engineering.
View ArticleFusing Implementation And Verification
Susantha Wijesekara, senior application engineer at Synopsys, drills down into how to re-use Tcl scripts for static verification, what needs to be done with those scripts to make that possible, why...
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Domain Crossing Nightmares
Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for...
View ArticleConstraint-Based Verification Of Clock Domain Crossings
There are many measures of the ever-growing size and complexity of semiconductor devices: die area, transistor count, gate count, size of memories, amount of parallel processing and more. All these...
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So Many Waivers Hiding Issues
Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for...
View ArticleClik here to view.
The Impact of Domain Crossing on Safety
Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for...
View ArticleClock Domain Crossings in the FPGA World
Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC issues on design functionality grows...
View ArticleClik here to view.
Adding Order And Structure To Verification
You can’t improve what you can’t measure, and when it comes to methodologies the notion of measurement becomes more difficult. Add in notions of the skills, capabilities and experience levels of...
View ArticleClik here to view.
FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis...
Increasing power constraints have resulted in finer-grained partitioning of designs into functional domains that can have clocks disabled or, more drastically, are powered down entirely. Systems are...
View ArticleSignoff-Compatible CDC
Tanveer Singh, senior staff consulting applications engineer at Synopsys, explains why netlist clock domain crossing is now an essential complement to RTL CDC, why CDC issues are worse at advanced...
View ArticleClik here to view.
Clock Domain Crossing Signoff Through Static-Formal-Simulation
By Sudeep Mondal and Sean O’Donohue Clocking issues are one of the most common reasons for costly design re-spins. This has been the driving factor in the ever-increasing demand for Clock Domain...
View Article