An Integrated Approach To Power Domain And Clock Domain Crossing Verification
Reducing power consumption is essential for both mobile and data center applications. The challenge is to lower power while minimally impacting performance. The solution has been to partition designs...
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Taming Non-Predictable Systems
How predictable are semiconductor systems? The industry aims to create predictable systems and yet when a carrot is dangled, offering the possibility of faster, cheaper, or some other gain, decision...
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An Integrated Approach To Power Domain And CDC Verification
Reducing power consumption is essential for both mobile and data center applications. Yet it is a challenge to lower power while minimally impacting performance. The solution has been to partition...
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Early Simulation Of Multi-Cycle Paths And False Paths
Designing with synchronous clocks avoids metastability issues on clock domain crossings, but it presents its own challenges when multi-cycle and false paths are involved. A multi-cycle path (MCP)...
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Clocks Getting Skewed Up
At a logical level, synchronous designs are very simple and the clock just happens. But the clocking network is possibly the most complex in a chip, and it’s fraught with the most problems at the...
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Formal Verification Ensures The Perseverance Rover Lands Safely On Mars
By Joe Hupcey III and Kevin Campbell Safely landing a spacecraft anywhere on Mars is a complex, high-risk challenge. Even worse, the most scientifically interesting areas of the planet are guarded by...
View ArticleRaising IP Integration Up A Level
An increase in the number and complexity of IP blocks, coupled with changing architectures and design concerns, are driving up the need for new tools that can enable, automate, and optimize integration...
View ArticleAchieve 10X Faster CDC Debug Leveraging Machine Learning
Over the years, system-on-chip (SoC) design sizes have crossed the billion-gate mark. Higher complexity has been introduced within semiconductor designs to deliver desired functionality. The number of...
View ArticleAccellera Preps New Standard For Clock-Domain Crossing
Part of the hierarchical development flow is about to get a lot simpler, thanks to a new standard being created by Accellera. What is less clear is how long will it take before users see any benefit....
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Accelerating Reset Domain Crossing Verification With Data Analytics Techniques
By Reetika and Sulabh Kumar Khare As the complexity of integrated circuit (IC) designs continues to rise, the task of verifying these designs has become increasingly challenging. The pace of this...
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